1. Field of the Invention
The present invention relates to a level conversion circuit capable of functioning as an interface between digital circuits having different power-supply voltages and a semiconductor integrated circuit in which the level conversion circuit is incorporated.
2. Description of the Prior Art
An allowable breakdown voltage of a gate oxide film has been lowered as the process for manufacturing MOS transistors is miniaturized. The breakdown voltage is about 4 V in miniaturized process of about 0.6 .mu.m. No trouble is caused if the gate oxide film is applied to circuits which are driven by the 3.3 V power supply, but the gate oxide film cannot be used in ordinary logical circuits driven by the 5 V power supply which has been used popularly in the prior art. Accordingly, the semiconductor integrated circuit including the gate oxide film whose breakdown voltage is lower than 5 V cannot help being driven by an around 3.3 V power supply.
In the event that a combination of 3.3 V power-supply system integrated circuits and 5 V power-supply system integrated circuits is used, signal transmission from the low voltage power-supply system to the high voltage power-supply system has not been easy. In the prior art, level conversion of the signal transmitted from the low voltage power-supply system to the high voltage power-supply system has been accomplished by virtue of the following techniques.
FIG. 1 is a circuit diagram showing a configuration of an ordinary level conversion circuit in the prior art (first conventional circuit).
As shown in FIG. 1, this level conversion circuit comprises two stage CMOS circuits which are connected between the 5 V power supply (VDD) and ground. A first stage CMOS circuit consists of a P-channel MOS transistor (referred simply to as "P-MOS" hereinafter) 101 and an N-channel MOS transistor (referred simply to as "N-MOS" hereinafter) 102. A second stage CMOS circuit consists of a P-MOS 103 and an N-MOS 104.
The N-MOS 102 is turned ON if an input signal IN1 of 3 V ("1" level) is input, and simultaneously the N-MOS 104 is turned OFF since an input signal IN2 of 0 V ("0" level) is input. The P-MOS 103 is turned ON by the ON state of the N-MOS 102 and then the P-MOS 101 is turned OFF by the ON state of the P-MOS 103. Therefore, output signals OUT1 and OUT2 are at 5 V and 0 V respectively.
Then, the N-MOS 102 is turned OFF if a level of the input signal IN1 is changed from 3 V to 0 V, and simultaneously the N-MOS 104 is turned ON since a level of the input signal IN2 is changed from 0 V to 3 V. The P-MOS 101 is turned ON by the ON state of the N-MOS 104 and, as a result, the P-MOS 103 is turned OFF. Therefore, output signals OUT1 and OUT2 are at 0 V and 5 V, respectively.
In this manner, level conversion from the 3.3 V power-supply system to the 5 V power-supply system has been conducted in this level conversion circuit.
FIG. 2 is a circuit diagram showing a configuration of a level conversion circuit disclosed in the Patent Application Publication (KOKAI) 4-150411 (second conventional circuit).
As shown in FIG. 2, this level conversion circuit comprises a latch circuit 200 having the high voltage (VDD: 5 V) power supply. N-MOSs 211, 212 are connected between nodes N11, N12 of the latch circuit 200 and ground respectively. An input signal IN of low voltage (VCC: 3 V) power-supply system is input to a gate of the N-MOS 211. An inverted signal of the input signal IN is input to a gate of the N-MOS 212 via an inverter 213 having a low voltage (VCC: 3 V) power-supply system.
Under the condition that the nodes N11, N12 of the latch circuit 200 are at 5 V, 0 V respectively, if the input signal IN goes to 3 V ("1" level), the N-MOS 211 is turned ON while the N-MOS 212 is turned OFF. As a result, since potential of the node N11 is shifted to 0 V, an output signal OUT which is kept at 5 V ("1" level) can be derived from the node N12 of the latch circuit 200.
FIG. 3 is a circuit diagram showing a configuration of a level conversion circuit disclosed in U.S. Pat No. 5,300,832 (third conventional circuit).
By making use of MOS transistors only in which the breakdown voltage of the gate oxide film is lower than the high voltage power supply (5 V), this level conversion circuit may execute level conversion of the signal from the low voltage power-supply system to the high voltage power-supply system.
As shown in FIG. 3, this level conversion circuit comprises a level conversion portion which is made up of MOS transistors 300 to 313 and an output portion which is made up of MOS transistors 314 to 317. The level conversion circuit receives an input signal IN of the low voltage (VCC: 3 V) power-supply system and then outputs level conversion controlling signals to nodes N21, N22. The output portion, if it receives the controlling signals from the level conversion portion, outputs an output signal OUT1 of 0 V to 5 V as a signal of the high voltage (VDD: 5 V) power-supply system, and an output signal OUT2 of intermediate potential to 5 V, and further an output signal OUT3 of 0 V to intermediate potential.
If the input signal IN goes to "0" level, the P-MOSs 306, 307 are turned ON to pull up nodes N23, N24. The N-MOS 304 is turned ON according to "1" level of the node N23, so that a current path via the P-MOS 301 and the N-MOS 302 can be constituted. As a result, a node N25 is pulled down to cause turning ON of the P-MOS 308.
If the P-MOS 308 is turned ON, not only the node N21 goes to "1" level but also a current path passing through the P-MOS 309 and the N-MOSs 310, 311 is constituted, and therefore the node N22 also goes to "1" level. As a result, the P-MOS 314 is turned OFF while the N-MOS 317 is turned ON. The output signals OUT1 and OUT3 are at 0 V and the output signal OUT2 is at intermediate potential.
Meanwhile, if the input signal IN goes to "1" level, the N-MOSs 305, 312 are turned ON to pull down potential of the nodes N22, N23. The N-MOS 317 is turned OFF because of pull-down of the node N22. If potential of the node N21 becomes lower than VDD (5 V), the P-MOS 314 is turned ON. The output signals OUT1 and OUT2 are at 5 V and the output signal OUT3 is at intermediate potential.
However, the following problems have existed in the level conversion circuit in the prior art.
More particularly, in the first conventional circuit (FIG. 1), since a voltage of the high voltage power-supply level is applied to gates of all MOS transistors which constitute the level conversion circuit, the breakdown voltage of the gate oxide film has to exceed the high voltage power-supply level. Therefore, the high breakdown voltage MOS transistors in which the gate oxide films are made thicker and the gate lengths are made longer must be formed partially on a chip of the integrated circuit as the level conversion circuit. This structure needs complicated manufacturing processes.
Similarly, in the second conventional circuit (FIG. 2), respective transistors of two inverters constituting the latch circuit 200 and the N-MOSs 211 and 212 have to be made of the transistors whose gate oxide films have the breakdown voltage higher than the high voltage power-supply level.
For contrast, in the third conventional circuit (FIG. 3), unlike the first and second conventional circuits, the level conversion circuit may be composed of only the transistors in which the breakdown voltage of the gate oxide film is lower than the high voltage power-supply level. However, in order to suppress the breakdown voltage of the gate oxide film of the P-MOS 314 less than the high voltage power-supply level (VDD), an amplitude of the gate voltage (node N21) of the P-MOS 314 is limited by virtue of an OFF effect of the P-MOS 309. In other words, because potential VB is supplied to the gate of the P-MOS 309, potential of the node N21 cannot be lowered to "0" level, but it can be reduced merely up to VB+V.sub.th (where V.sub.th is a threshold voltage of the P-MOS). With the use of a phenomenon that potential of the node N21 is naturally stabilized at VB+V.sub.th according to OFF of the P-MOS 309, an amplitude of the gate voltage of the P-MOS 314 is limited. For this reason, such a problem has existed that high speed operation of the level conversion circuit cannot be achieved. In addition, if the P-MOS 314 is in the ON state, the gate voltage (potential of the node N21) becomes VDD-(VB+V.sub.th) and therefore, if VB+V.sub.th is higher than 3 V, this gate voltage becomes a low value. Accordingly, another problem has also existed that load driving capability of the output portion is reduced.